<div class="content-intro"><h1 style="text-align: center;"><span style="color: rgb(230, 126, 35); font-family: georgia, palatino, serif;"><strong data-redactor-tag="strong">Build to something to be proud of.</strong></span></h1><hr><p style="text-align: center;"><span style="font-family: verdana, geneva, sans-serif; font-size: 10pt;">Captivation has built a reputation on providing customers exactly what is needed in a timely manner. Our team of engineers take pride in what they develop and constantly innovate to provide the best solution. Captivation is looking for software developers who can get stuff done while making a difference in support of the mission to protect our country.</span></p><p> </p></div><h1 style="text-align: center;"><span style="color: rgb(230, 126, 35); font-family: georgia, palatino, serif;">Description</span></h1><hr><p><span style="font-family: verdana, geneva, sans-serif; font-size: 10pt;">Captivation Software is looking for a senior level signals processing engineer who will assist with daily responsibilities to support the program. </span></p><p> </p><h1 style="text-align: center;"><span style="color: rgb(230, 126, 35); font-family: georgia, palatino, serif;">Responsibilities</span></h1><hr><ul><li style="font-size: 10pt; font-family: verdana, geneva, sans-serif;">Provides concise explanation of developed models to allow other team members to understand/utilize models or algorithms for processing signals of interest.</li><li style="font-size: 10pt; font-family: verdana, geneva, sans-serif;">Develops, tests, and implements digital signal processing algorithms for satellite communication systems.</li><li style="font-size: 10pt; font-family: verdana, geneva, sans-serif;">Collaborate with infrastructure engineers and software engineers to integrate DSP software into overall system architecture</li></ul><p> </p><h1 style="text-align: center;"><span style="color: rgb(230, 126, 35); font-family: georgia, palatino, serif;">Requirements</span></h1><hr><h3><span style="font-family: georgia, palatino, serif;">Security Clearance:</span></h3><ul><li style="font-family: verdana, geneva, sans-serif; font-size: 10pt;"><span style="font-family: verdana, geneva, sans-serif; font-size: 10pt;">Must currently hold a Top Secret/SCI U.S. Government security clearance with a favorable Polygraph, therefore all candidates must be a U.S. citizen</span></li></ul><h3><span style="font-family: georgia, palatino, serif;">Minimum Qualifications:</span></h3><ul><li style="font-family: verdana, geneva, sans-serif; font-size: 10pt;">Ten (10) years experience as a DSP Algorithm developer is required.</li><li style="font-family: verdana, geneva, sans-serif; font-size: 10pt;">Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science from an accredited college or university is required</li></ul><h3><span style="font-family: georgia, palatino, serif;">Required Skills:</span></h3><ul><li style="font-family: verdana, geneva, sans-serif; font-size: 10pt;">RF signals analysis</li><li style="font-family: verdana, geneva, sans-serif; font-size: 10pt;">Demonstrated experience coding C/C++ and Python</li><li style="font-family: verdana, geneva, sans-serif; font-size: 10pt;">Able to design, develop and implement systems within a Unix/Linux environment</li><li style="font-family: verdana, geneva, sans-serif; font-size: 10pt;">Experience with message queue implementation/communication</li></ul><h3><span style="font-family: georgia, palatino, serif;">Desired Skills:</span></h3><ul><li style="font-family: verdana, geneva, sans-serif; font-size: 10pt;"><span style="font-family: verdana, geneva, sans-serif; font-size: 10pt;">Digital Signal Processing background with strong understanding of satellite communications system design and theory with implementation of concepts into software</span></li><li style="font-family: verdana, geneva, sans-serif; font-size: 10pt;"><span style="font-family: verdana, geneva, sans-serif; font-size: 10pt;">Experience with DSP hardware and software development tools such as DSP processors, development kits, and IDEs</span></li><li style="font-family: verdana, geneva, sans-serif; font-size: 10pt;"><span style="font-family: verdana, geneva, sans-serif; font-size: 10pt;">Experience with FPGA, microcontroller, or ASIC design</span></li><li style="font-family: verdana, geneva, sans-serif; font-size: 10pt;"><span style="font-family: verdana, geneva, sans-serif; font-size: 10pt;">Familiarity with implementation and integration of SDR technologies into virtual (VMWare) and containerized (Docker/K8) environments</span></li><li style="font-family: verdana, geneva, sans-serif; font-size: 10pt;"><span style="font-family: georgia, palatino, serif;"><span style="font-family: verdana, geneva, sans-serif; font-size: 10pt;">Experience with Development Suites (MATLAB, X-Midas, etc.)​</span></span></li></ul><p> </p><p style="text-align: center;"><span style="font-family: verdana, geneva, sans-serif; font-size: 10pt;"><em><strong>This position is open for direct hires only. We will not consider candidates from third party staffing/recruiting firms.</strong></em></span></p><div class="content-conclusion"><h1 style="text-align: center;"><span style="color: rgb(230, 126, 35); font-family: georgia, palatino, serif;">Benefits</span></h1><hr><ul><li style="text-align: left; font-size: 10pt;"><span style="font-family: verdana, geneva, sans-serif; font-size: 10pt;">Annual Salary: $130,000 - $270,000 (Depends on the Years of Experience)</span></li><li style="text-align: left; font-size: 10pt;"><span style="font-family: verdana, geneva, sans-serif; font-size: 10pt;">Up to 20% 401k contribution (No Matching Required and Vested from Day 1)</span></li><li style="text-align: left; font-size: 10pt;"><span style="font-family: verdana, geneva, sans-serif; font-size: 10pt;">Above Market Hourly Rates</span></li><li style="text-align: left; font-size: 10pt;"><span style="font-family: verdana, geneva, sans-serif; font-size: 10pt;">$3,400 HSA Contribution</span></li><li style="text-align: left; font-size: 10pt;"><span style="font-family: verdana, geneva, sans-serif; font-size: 10pt;">6 Weeks Paid Time Off</span></li><li style="text-align: left; font-size: 10pt;"><span style="font-family: verdana, geneva, sans-serif; font-size: 10pt;">Company Paid Employee Medical/Dental/Vision Insurance/Life Insurance/Short-Term & Long-Term Disability/AD&D</span></li></ul><p> </p></div>